1. Field of the Invention
The present invention relates to a packaging structure for packaging a semiconductor device on a wiring board and its mounting method, and more particularly to a packaging structure for packaging a semiconductor device according to flip-chip method and its packaging method.
2. Description of the Prior Art
In recent years, the structure for packaging semiconductor devices on a wiring board with high density is being simplified accompanying the reduction in the size and cost of the electronic equipment. As a high density packaging structure for the semiconductor devices having such a simplified constitution, there is proposed a flip-chip method.
The packaging structure for the semiconductor device according to the conventional flip-chip method is disclosed in a paper entitled "Leadless Bare Chip Packaging Technology and Its Application to MCM-L", Mate "96, February, 1996, pp. 193-196 and in a paper entitled "General Electronic Components for Packaging", Nikkei Micro-devices, March issue, March, 1996, pp. 146-147.
In the conventional packaging structure for the semiconductor device as shown in FIG. 10, a semiconductor chip 1 is packaged on a wiring board 4 in flip-chip mode, and Au bumps 3 on chip electrodes 2 and solder bumps 6 on board electrodes 5 are connected with each other. Further, a sealing resin 15 is filled in the gap between the semiconductor chip 1 and the wiring board 4, where a filler material such as spherical silica (SiO.sub.2) is uniformly dispersed in the sealing resin.
In the conventional packaging structure for the semiconductor device, when a printed board having a glass epoxy as the base material is used as the wiring board, the coefficients of thermal expansion of the printed board and the semiconductor chip which is generally made of silicon, with values of about 3.times.10.sup.-6 m/.degree. C. and about 14.times.10.sup.-6 m/.degree. C., respectively, differ to a large extent. The large difference of the coefficient of thermal expansion gives rise to a stress in connection parts of the electrodes and the bumps of respective components. If a resin is used as the material for the wiring board, the difference in the coefficient of thermal expansion is further increased and the stress is increased correspondingly. Accordingly, it becomes necessary to reduce the coefficient of thermal expansion of the sealing resin after curing in order to relax the stress in the connection parts. In order to suppress the coefficient of thermal expansion of the sealing resin to a smaller range, it is necessary to mix a filler, such as spherical silica, which is a material of low coefficient of thermal expansion, to a base resin of the sealing resin.
However, an increase in mixing ratio of the filler leads to problems such as those in the following. Namely, when the mixing ratio of the filler in the sealing resin is increased, the overall viscosity of the resin goes up. In filling the sealing resin into the gap between the semiconductor chip and the wiring board, the capillary phenomenon is generally utilized. So when the viscosity of the resin becomes high, there is required a longer time for filling the resin and the productivity is deteriorated. Moreover, in a structure of fine pad pitch smaller than 120 .mu.m, filling of the sealing resin may become impossible when the viscosity of the sealing resin is too high.
Furthermore, when the mixing ratio of the filler in the sealing resin is raised, the area, over which the base resin of the sealing resin is adhered to the circuit plane of the semiconductor chip, becomes small due to the presence of a large number of filler particles on the circuit plane of the semiconductor chip. Accordingly, the adhesive power to the semiconductor chip of the sealing resin becomes small, which results in such problems as defective connection parts and corrosion of aluminum in the chip pads.